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BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Rev. 02 -- 21 January 2008 Product data sheet
1. Introduction
This data sheet describes a family of integrated circuits which provide direct digital control of multiple power switches (TrenchPLUS FETs) for use in automotive applications, and which are available in various configurations.
2. General description
Eight channel high-side switch controller in a leaded plastic quad flat package, with digital control and diagnostics, plus load current measurement. Specific configurations are denoted by the last 2 letters in the type number.
3. Features
I I I I I I I I I I I I I I Standby mode with very low power consumption Programmable drain current tripping Serial Peripheral Interface (SPI) communications Outputs controllable via SPI-bus or direct input Diagnostic status reporting via SPI-bus Analog and digital drain current measurement Watchdog for invalid commands or inactive SPI, with programmable time-out Programmable interrupt generator Overtemperature protection Pulse-width modulation with programmable frequency and duty cycle ESD protection on all pins Protection for battery transient overvoltage and reversed polarity battery connection Open-circuit detection Configurable fail-safe channel control options
4. Applications
I Automotive applications such as DC and pulse-width modulation control in body control clusters, etc.
NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
5. Quick reference data
Table 1. Symbol VBAT Tj
[1] [2]
Quick reference data Parameter battery supply voltage junction temperature Conditions operating
[1] [2]
Min 5.5 -40
Typ 13 -
Max 52 +150
Unit V C
When VBAT < 9 V, the charge pump cannot be guaranteed to drive the external MOSFETs to achieve their specified RDSon. When Tj > 125 C, the device will function, but electrical parameters may deviate from the specified values.
6. Ordering information
Table 2. Ordering information Package Name BUK3F00-50WDFM BUK3F00-50WDFY Description Version Type number
BUK3F00-50WDFE QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1
6.1 Ordering options
Table 3. Type number differences Description channel 4 has analog trip ratio of 3 x Imeas(ADC)(fs)[1] Type number BUK3F00-50WDFE BUK3F00-50WDFM BUK3F00-50WDFY
[1]
Imeas(ADC)(fs) = full-scale ADC measure current.
User-accessible registers; see Table 5. Protected settings; see Table 19. Additional metal mask options; see Table 35.
BUK3F00-50WDXX_2
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Product data sheet
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Controller for TrenchPLUS FETs
7. Block diagram
VBAT
VBAT 7
VBAT(CP) 42
CPN 41
CPP CT GND(CP) 40 39 43
VCC(MOD) VCC(LOG)EXT VCC(DIGC) GND(DIGC) VCC(MEASC)
10 44 38 37 6
anode 0 to 7 SUPPLIES CHARGE PUMP POWER AND REFERENCE SUPPLIES REFERENCE SUPPLIES
GND 1, 16, 33, 48 IREFCURR 8 IREFTEMP 9
TEMPERATURE SENSE
BUK3F00-50WDXX
gate 0 to 7 TrenchPLUS FET INTERFACE (8x) sense 0 to 7 EXTERNAL TrenchPLUS FET SWITCHES (8x)
WDEN WDTON SCSN SDI SDO SCLK EN IN0 IN1 IN2 IN3 INP
15 2 35 36 45 34 11 3 4 13 12 14 PULSE-WIDTH MODULATION (PWM) INTERRUPT SERIAL PERIPHERAL INTERFACE (SPI)
SPI WATCHDOG
CURRENT SENSE DIGITAL CONTROL kelvin 0 to 7
PWMMON
47
INTN
46
cathode 0 to 7 CURRENT MEASUREMENT
001aaf047
CONTROL LOGIC IMEAS 5
Fig 1. Block diagram
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BUK3F00-50WDXX
Controller for TrenchPLUS FETs
8. Pinning information
8.1 Pinning
61 KELVIN0 57 KELVIN1 53 KELVIN2 49 KELVIN3 48 GND 47 PWMMON 46 INTN 45 SDO 44 VCC(LOG)EXT 43 GND(CP) 42 VBAT(CP) 41 CPN 40 CPP 39 CT 38 VCC(DIGC) 37 GND(DIGC) 36 SDI 35 SCSN 34 SCLK 33 GND KELVIN7 17 ANODE7 18 SENSE7 19 GATE7 20 KELVIN6 21 ANODE6 22 SENSE6 23 GATE6 24 KELVIN5 25 ANODE5 26 SENSE5 27 GATE5 28 KELVIN4 29 ANODE4 30 SENSE4 31 GATE4 32
001aaf048
62 ANODE0
58 ANODE1
54 ANODE2
GND WDTON IN0 IN1 IMEAS VCC(MEASC) VBAT IREFCURR IREFTEMP
1 2 3 4 5 6 7 8 9
BUK3F00-50WDXX
VCC(MOD) 10 EN 11 IN3 12 IN2 13 INP 14 WDEN 15 GND 16
Fig 2. Pin configuration
8.2 Pin description
Table 4. Symbol Supplies VBAT GND VBAT(CP) GND(CP) VCC(DIGC) GND(DIGC) VCC(MOD) VCC(LOG)EXT VCC(MEASC) 7 1, 16, 33, 48 42 43 38 37 10 44 6 battery supply voltage battery ground charge pump battery supply voltage charge pump ground digital core supply voltage digital core ground module supply voltage external logic supply voltage for PWMMON and SDO outputs measurement circuit supply voltage Pin description Pin Description
BUK3F00-50WDXX_2
50 ANODE3
63 SENSE0
59 SENSE1
55 SENSE2
51 SENSE3
64 GATE0
60 GATE1
56 GATE2
52 GATE3
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Product data sheet
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Controller for TrenchPLUS FETs
Pin description ...continued Pin 40 41 39 11 46 15 2 47 34 35 36 45 8 9 5 3 4 13 12 14 Description positive connection to external pump capacitor negative connection to external pump capacitor connection to external storage capacitor enable input; internal pull-down resistor interrupt output; open-drain output watchdog enable input; internal pull-up resistor watchdog timed output; open-drain output PWM frequency monitor output SPI clock input; internal pull-down resistor SPI chip select input; internal pull-up resistor SPI data input; internal pull-down resistor SPI data output; 3-state when inactive set reference for current measurement (with external resistor) set reference for temperature sense (with external resistor) analog current measurement output (for selected channel) direct input 0; internal pull-down resistor direct input 1; internal pull-down resistor direct input 2; internal pull-down resistor direct input 3; internal pull-down resistor PWM input; internal pull-down resistor
Table 4. Symbol CPP CPN CT Digital EN INTN WDEN WDTON PWMMON SCLK SCSN SDI SDO Analog
Charge pump capacitors
Serial peripheral interface
IREFCURR IREFTEMP IMEAS IN0 IN1 IN2 IN3 INP Channel 0 GATE0 KELVIN0 SENSE0 ANODE0 Channel 1 GATE1 KELVIN1 SENSE1 ANODE1 Channel 2 GATE2 KELVIN2 SENSE2 ANODE2
BUK3F00-50WDXX_2
Direct input pins
Connections for external TrenchPLUS switches 64 61 63 62 60 57 59 58 56 53 55 54 gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode
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Product data sheet
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Controller for TrenchPLUS FETs
Pin description ...continued Pin 52 49 51 50 32 29 31 30 28 25 27 26 24 21 23 22 20 17 19 18 Description gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode gate source kelvin current sense anode of temperature sense diode
Table 4. Symbol Channel 3 GATE3 KELVIN3 SENSE3 ANODE3 Channel 4 GATE4 KELVIN4 SENSE4 ANODE4 Channel 5 GATE5 KELVIN5 SENSE5 ANODE5 Channel 6 GATE6 KELVIN6 SENSE6 ANODE6 Channel 7 GATE7 KELVIN7 SENSE7 ANODE7
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Controller for TrenchPLUS FETs
9. Functional description
The main functions of the device are:
* * * * *
Power and reference supplies Charge pump Control logic Current measurement TrenchPLUS FET interface (8 x)
9.1 Power and reference supplies
The main battery supplies power to the device and the eight TrenchPLUS FET switches. This device is intended for vehicle system applications that operate at a battery voltage of 12 V, 24 V or 42 V. The device has several different supply connections to ensure correct operation of the device within the application module.
9.1.1 Battery supply: pins VBAT and GND
Pins VBAT and GND are the direct supply connections of the device to the battery. Low battery voltage is detected on the charge pump supply pin VBAT(CP). Channels are switched off during extended low battery supply conditions and switched on when normal battery conditions return. Extended low battery voltage occurs when the battery supply voltage VBAT goes below:
* the battery undervoltage threshold (Vth(uv)bat) for longer than the battery low time
(tlow(bat)), or
* the battery low threshold voltage (Vth(low)bat)
Transient low battery voltage occurs when the battery supply voltage VBAT goes below Vth(uv)bat for less than tlow(bat), but remains above Vth(low)bat. Transient low battery voltage conditions affect the overcurrent protection; for details see Section 9.5.2 "Overcurrent protection". Normal battery voltage occurs when the battery supply voltage exceeds Vth(uv)bat for more than the battery high time (thigh(bat)). Hysteresis on detection reduces the possibility of repeated switching when the battery supply voltage is close to the threshold values. The supply circuit has an internal overvoltage clamp to protect the control IC from overvoltage transients and is also protected against ESD. All four GND pins must be connected together to ground. If this supply is connected to a reverse polarity battery voltage then the FET switches are turned on to protect against conduction through the source-drain diode. This protection operates whether the device is enabled or not.
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Product data sheet
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Controller for TrenchPLUS FETs
9.1.2 Module supply: pins VCC(MOD) and GND
Pins VCC(MOD) and GND supply power to the circuits in the device that need to be kept functioning when the main battery supply dips below its normal operating limit. It is anticipated that the connection will be to the protected supply of the application module control circuits. This can be created using a suitable diode and storage capacitor from the battery supply. The connection should be decoupled close to the device. Low module voltage causes the device to go through a Power-On Reset (POR). This condition is detected when the module supply voltage goes below the module undervoltage threshold (Vth(uv)mod). The power-on reset is triggered when the supply voltage recovers and exceeds Vth(uv)mod. Hysteresis on this detection reduces the possibility of repeated resetting when the module supply is close to the threshold value. The supply circuit has an internal overvoltage clamp to protect the control chip from overvoltage transients and is also protected against ESD. This supply should be protected against reverse battery connection in the application circuit.
9.1.3 External logic supply: pins VCC(LOG)EXT and GND
The external logic supply provides power for the SDO and PWMMON output pins. Pin VCC(LOG)EXT should be connected to the same supply (3.3 V or 5 V) used by the circuits that monitor these outputs.
9.1.4 Analog measurement supply: pins VCC(MEASC) and GND
This supply provides power for the IMEAS analog current measurement output. Pin VCC(MEASC) should be connected to the same supply (3.3 V or 5 V) used by the circuit that uses this output. If this output is not needed, then pins VCC(MEASC) and IMEAS should be grounded.
9.1.5 Digital supply: pins VCC(DIGC) and GND(DIGC)
This supplies power to the internal regulator for the digital core and should be connected to the same potential as VCC(MOD) and GND. It is not internally connected to the module supply, ensuring that digital noise does not affect the measurement circuits. The connection should be decoupled close to the device. The digital supply circuit has an internal overvoltage clamp to protect the BUK3F00-50WDXX from overvoltage transients and is also protected against ESD.
9.1.6 Reference supplies: pins IREFCURR and IREFTEMP
An internal band gap reference is used to ensure stable voltage and current references:
* Measured current reference pin IREFCURR: The full-scale analog output
measurement current and the full-scale measurement current through the ADC are both set by connecting an external resistor between pins IREFCURR and GND.
* Temperature reference pin IREFTEMP: The forward current for the temperature
sensing diodes in the TrenchPLUS FETs is set by connecting an external resistor between pins IREFTEMP and GND.
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Product data sheet
Rev. 02 -- 21 January 2008
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Controller for TrenchPLUS FETs
9.2 Charge pump
The controller has an internal charge pump circuit to supply the gate voltage required to operate the high-side FET switches. The charge pump uses an internal oscillator and internal switches with external pump and storage capacitors.
9.2.1 Charge pump supply: pins VBAT(CP) and GND(CP)
Pins VBAT(CP) and GND(CP) supply power to the internal charge pump. This is derived from the VBAT supply either via an internal resistor between pins VBAT and VBAT(CP) or by linking these pins externally. Pin GND(CP) should be connected to pin GND; the grounds are not internally connected to ensure any charge pump noise does not affect the measurement circuit. The connections should be decoupled close to the device. The charge pump supply circuit has an internal overvoltage clamp to protect the BUK3F00-50WDXX from overvoltage transients and is also protected against ESD. If connected to a reverse polarity battery voltage, the charge pump supply is protected by the internal resistor connection to VBAT.
9.2.2 Charge pump boost mode
To ensure fast start-up, the charge pump has a boost mode that operates for a set time. This mode is triggered at power-on reset and when the charge pump voltage falls below the charge pump fault threshold or the battery voltage stays below the undervoltage threshold. If the charge pump voltage is below the fault threshold after the charge pump boost is completed, then no further boost is possible until the charge pump fault is cleared.
9.3 Control logic
The control logic is responsible for switching the individual FET channels on and off, depending on user settings and the implementation of protection methods. It contains registers used for storing the user settings for channel configurations, current reference and measurement, diagnostic and watchdog modes. Communication with a controller is via the SPI-bus. The digital block is designed to support 8 channels; unused channels should be programmed off at all times.
9.3.1 Digital control
The device is enabled by pin EN. When pin EN is LOW, the device is in Standby mode and all FETs are held off by an active switch with a standby resistance between pins GATE and KELVIN. When pin EN is HIGH, the device is enabled for normal operation. Pin EN can be used as the reset signal by a controller for the control logic. When pin EN is reset to HIGH, the device goes through a power-on reset, registers are loaded with their default values and channels are switched on or off according to the mapping for the individual device type. Digital control consists of a number of registers that control the functions. The default value is loaded during power-on reset and, if the WRITE_PROTECT option is enabled, for defined registers, when the SPI watchdog times out. For some registers the default setting can be programmed by metal mask options.
BUK3F00-50WDXX_2
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Product data sheet
Rev. 02 -- 21 January 2008
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BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Table 5. Register[1]
User-accessible registers Name Description Mask Version default value[2] option FE FM FY N Y[4] Y[4] Y[4] Y[4] N Y[4] Y[4] N N Y[4] Y[4] Y[4] Y[4] Y[4][5] Y[4][5] Y[4][5] Y[4][5] Y[4][5] Y[4][5] Y[4][5] Y[4][5] Y[4] Y[4] Y[4] Y[4] N[4] N[4] N[4] N[4] N[4] N[4] N[4] N[4] Y[4] Y[4] N 00h 21h 84h 10h 00h 00h 00h 00h 00h FFh 21h 3Fh 08h B6h FFh FFh FFh FFh FFh FFh FFh FFh AAh AAh AAh AAh FFh FFh FFh FFh FFh FFh FFh FFh 04h 2Fh FFh 00h 10h 40h 08h 00h 00h 00h 00h 00h FFh 58h 3Fh 08h BBh FFh FFh FFh FFh FFh FFh FFh FFh AAh AAh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh 19h 2Fh FFh 00h 1Ch 01h 00h 00h 00h 00h 00h 00h FFh 1Dh 3Fh 08h B1h FFh FFh FFh FFh FFh FFh FFh FFh AAh AAh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh 00h 2Fh FFh
Read/write registers[3] 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
BUK3F00-50WDXX_2
CHAN_ONOFF IN02_MAP IN13_MAP INP_MAP ANDOR_MAP CURR_MEAS SEL_CURR_TRIP_ CHAN CHAN_OT_FAULT_CLR PWM_SYNC PWM_SAM_BEGINEND CHAN_WD_MAP WD_TO CTRL_SET INT_PWM_FREQ PWM_DC_CH0 PWM_DC_CH1 PWM_DC_CH2 PWM_DC_CH3 PWM_DC_CH4 PWM_DC_CH5 PWM_DC_CH6 PWM_DC_CH7 OT_TRIPLEV_CH30 OT_TRIPLEV_CH74 IFSC_CH30 IFSC_CH74 CURR_TRIPLEV_CH0 CURR_TRIPLEV_CH1 CURR_TRIPLEV_CH2 CURR_TRIPLEV_CH3 CURR_TRIPLEV_CH4 CURR_TRIPLEV_CH5 CURR_TRIPLEV_CH6 CURR_TRIPLEV_CH7 IRQ_MAP CURR_TRIP_ BLANKTIME OLDET_ONOFF
channels select: on/off direct input pins IN0 and IN2 mapping direct input pins IN1 and IN3 mapping PWM input pin INP mapping direct input pin AND/OR operation channel select analog current measurement select current tripping channel channel set overtemperature fault clear channel PWM synchronization channel PWM sample point begin or end select channel watchdog behavior watchdog time-out period setting controller settings internal PWM frequency setting internal PWM duty cycle setting for channel 0 internal PWM duty cycle setting for channel 1 internal PWM duty cycle setting for channel 2 internal PWM duty cycle setting for channel 3 internal PWM duty cycle setting for channel 4 internal PWM duty cycle setting for channel 5 internal PWM duty cycle setting for channel 6 internal PWM duty cycle setting for channel 7 overtemperature trip level channels 3 to 0 overtemperature trip level channels 7 to 4 full-scale reference current channels 3 to 0 full-scale reference current channels 7 to 4 current trip level for channel 0 current trip level for channel 1 current trip level for channel 2 current trip level for channel 3 current trip level for channel 4 current trip level for channel 5 current trip level for channel 6 current trip level for channel 7 interrupt request mapping current trip blanking time off-state open-circuit detection
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Product data sheet
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Controller for TrenchPLUS FETs
Table 5. Register[1] 27h 28h Write-only 29h 2Ah Read-only 30h 31h 32h 33h 34h 35h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
[1] [2] [3] [4] [5] [6] [7] [8] [9]
User-accessible registers ...continued Name READBACK IRQ_CHAN_MAP registers[6] CLEAR_CHAN_INTN CLEAR_WD registers[7] DIAG_BASIC DIAG_CTRL ISR VERSION DIAG_CHAN_01 DIAG_CHAN_02 DIAG_DETAIL_CH0 DIAG_DETAIL_CH1 DIAG_DETAIL_CH2 DIAG_DETAIL_CH3 DIAG_DETAIL_CH4 DIAG_DETAIL_CH5 DIAG_DETAIL_CH6 DIAG_DETAIL_CH7 basic diagnostics controller diagnostics interrupt status register device version number VOUTHIGH and VOUTLOW states[8] TSNSOPEN signal state[9] detail diagnostics; channel 0 detail diagnostics; channel 1 detail diagnostics; channel 2 detail diagnostics; channel 3 detail diagnostics; channel 4 detail diagnostics; channel 5 detail diagnostics; channel 6 detail diagnostics; channel 7 clear channels and interrupt clear watchdog state Description register and diagnostic read back interrupt generating channels Mask Version default value[2] option FE FM FY N N[4] 30h FFh 30h FFh 30h FFh
This column denotes either the address used to write to the indicated register, or the data sent to register READBACK (27h) to read back from the indicated register. Default values for read/write registers are either fixed or programmable as mask options for individual types. 8-bit read/write registers store settings that control the behavior of the device. Default values are stored at power-on reset and data can be changed via SPI-bus communication. To help provide security of operation these registers can also be read back. Another metal mask option is available, which means that WRITE_PROTECT is set. CHAN_WD_MAP and WD_TO registers are write-protected by this option. The other registers indicated will be reloaded with default values if an SPI watchdog time-out occurs. Only bit 7 is mask programmable. 8-bit write-only registers clear tripped channels, interrupt and watchdog states when data is written. The values are not stored and cannot be read back. 16-bit read-only registers contain data about the state of the device for diagnostic use. Data cannot be written to these registers. VOUTHIGH: high-side FET is in on-state for overcurrent protection (> Vth(on)(bat-KEL)). VOUTLOW: high-side FET output voltage is below the voltage required for open-circuit detection (< Vdet(oc)off). TSNSOPEN: temperature sensor open-circuit.
BUK3F00-50WDXX_2
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Product data sheet
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Controller for TrenchPLUS FETs
9.3.2 Serial Peripheral Interface (SPI)
The SPI is used for communication with a controller and provides control and diagnostic functions. The device is configured as an SPI slave. The interface consists of SPI Chip Select (SCSN), Serial Clock (SCLK), Serial Data In (SDI) and Serial Data Out (SDO). SPI communication is enabled when SCSN is set LOW. Data is shifted out to pin SDO on the SCLK rising edge. The data shifted out depends on which register is addressed by register READBACK (27h). Data is shifted in from pin SDI on the SCLK falling edge. The controller can be timed to send data to SDI on the SCLK rising edge with data valid on the falling edge. Data is valid for reading on the falling edge. For full timing requirements; see Table 25 "Recommended operating conditions" and Figure 9 "SPI timing definitions". SPI communication uses 16-bit words; see Figure 3. The most significant byte, the register address byte, is transferred first. The 2 most significant bits of the register address byte are not used, they must always be logic 0. The 6 least significant bits form the actual register address.
MSB 0
SPI communication word high byte low byte LSB MSB
LSB
0AAAAAADDDDDDDD address data
001aae996
Fig 3. SPI communication format; full 16-bit operation
When SCSN is set HIGH after a 16-bit valid communication, then the SDO output becomes inactive and goes to high-impedance. The data in the low byte is then transferred to the address given in the high byte. After this is completed the SPI shift register is refreshed with the latest contents of the register addressed by the entry in register READBACK. When 8-bit registers are read, the least significant byte is padded with 55h. Data is checked for validity after SCSN goes HIGH. It is valid if the count of SCLK negative edges is a multiple of 8 and the address part (high byte) of the 16-bit message contains a valid address. An invalid address will result in a value of 00h being sent on SDO. To allow time for validity checking, writing data and refreshing the shift register, SCSN must be disabled (HIGH) for a period tw(SCSN).
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SCSN
SCLK
SDI
MSB
LSB MSB
LSB
SDO
MSB high byte
LSB MSB low byte
LSB
001aaf575
Fig 4. SPI communication frame: full 16-bit operation
To support 8-bit microcontrollers an 8-bit operation is possible; see Figure 5. In this operation, SCSN is taken HIGH between the 8-bit bytes. SDO is taken HIGH before the SCLK of the low byte to indicate that the low byte is to be sent.
SCSN
SCLK
SDI
MSB
LSB
MSB
LSB
SDO
MSB high byte
LSB
MSB low byte
LSB
001aaf576
Fig 5. SPI communication frame: 8-bit operation
A number of devices can be daisy chained by connecting the SDO of the first device to the SDI of the next device and so on; see Figure 6. All devices have their SCSN inputs connected to the same controller chip select so that they can be selected together. When n devices are daisy chained, then n SPI 16-bit word cycles must be executed to program all devices. Daisy chaining cannot be used with 8-bit SPI operation.
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MCSN SCSN SLAVE1 SDI SDO MDO MDI
001aag750
MASTER
SCSN SLAVE2 SDI SDO SDI
SCSN SLAVE3 SDO
Fig 6. Daisy chain connection of three ASICs (requires three SPI 16-bit word cycles)
9.3.3 SPI watchdog
The SPI watchdog detects if there is a breakdown in the SPI communication with the controller. A timer is activated that resets when a valid communication is received. If no valid SPI communications are received within the specified time-out period, the watchdog will signal this to the control logic. The SPI watchdog is enabled either by setting pin WDEN = HIGH or by enabling watchdog active with bit WD_TO[5]. FET channels can be turned either on or off when a watchdog time-out occurs as set by register CHAN_WD_MAP. Pin WDTON is set LOW for a selectable period when a watchdog time-out occurs and can be used as a reset for the controller. An interrupt on pin INTN can also be set when a watchdog time-out occurs. Other functions of the device are not changed in Watchdog mode. In particular, if the SPI fault that caused the condition is resolved, SPI communication would work and diagnostics could be performed. See Section 11.1 "Reset for interrupt and SPI watchdog" for details of clearing watchdog states.
Table 6. Address 0Ch Select channel watchdog behavior register (address 0Ch) bit description Register CHAN_WD_MAP[1] Bit Description 7 to 0 behavior when watchdog time-out occurs in individual channels 7 to 0: 1 = turn selected channel on[2] 0 = turn selected channel off
[1] [2] A metal mask option WRITE_PROTECT is available, which means that registers are write protected. Provided channel is not mapped to a direct input pin. If channel is mapped to a direct input pin, then the channel will only turn on if the direct input pin is HIGH.
Table 7. Address 0Dh
Watchdog time-out period setting register (address 0Dh) bit description Register WD_TO Bit 7 to 6 5 4 to 0 Description not used enable watchdog watchdog time-out period; see Table 8
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Product data sheet
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Controller for TrenchPLUS FETs
Table 8. Watchdog time-out period Given times are valid for nominal master clock frequency. Time-out period Value 00h 01h 02h 03h 04h 05h 06h 07h Time 1.0 ms 1.3 ms 1.5 ms 1.8 ms 2.0 ms 2.6 ms 3.1 ms 3.6 ms Value 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Time 4.1 ms 5.1 ms 6.1 ms 7.2 ms 8.2 ms 10 ms 12 ms 14 ms Value 10h 11h 12h 13h 14h 15h 16h 17h Time 16 ms 20 ms 25 ms 29 ms 33 ms 41 ms 49 ms 57 ms Value 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Time 66 ms 82 ms 98 ms 115 ms 131 ms 164 ms 197 ms 229 ms
9.3.4 Pulse-Width Modulation (PWM)
PWM can be implemented on selected channels by either an internally generated signal or an externally connected signal. For the internally generated signal, it is possible to select frequency and duty cycle and to synchronize the selected channels. The internally generated signal is used when the duty cycle is set to less than 100 %. For both internal and external PWM signals it is possible to specify the point at which the FET current is sampled in the PWM period. An external PWM signal can be connected to the input pin INP (intended for normal PWM operation) or pins IN0 to IN3 (intended for fail-safe operation). The required channels are then mapped accordingly.
Table 9. Address 09h PWM setting registers (addresses 09h, 0Ah, 0Fh, 10h to 17h) bit description Register PWM_SYNC[1] Bit Description 1 = selected channel synchronized to previous channel in this mode 0 = selected channel one eighth of internal PWM cycle out of phase 0Ah PWM_SAM_ BEGINEND 7 to 0 PWM sample begin or end in individual channels 7 to 0[2]: 1 = selected channel set to end 0 = selected channel set to start 0Fh INT_PWM_FREQ[3] 7 to 0 internal PWM frequency setting for all channels: 00h to 3Fh: f = {code + 01h} x 0.125 Hz, from 0.125 Hz to 8.0 Hz in 0.125 Hz steps 40h to 7Fh: f = {code - 3Fh} x 0.5 Hz, from 0.5 Hz to 32.0 Hz, in 0.5 Hz steps 80h to BFh: f = {code - 7Fh} x 2.0 Hz, from 2.0 Hz to 128.0 Hz, in 2.0 Hz steps C0h to FFh: f = {code - BFh} x 8.0 Hz, from 8.0 Hz to 512.0 Hz, in 8.0 Hz steps 10h to 17h PWM_DC_CHn[3] 7 to 0 internal PWM duty cycle for specified channel 7 to 0; duty cycle = (n + 1) / 256, where n = decimal number set in register 7 to 0 PWM synchronization in individual channels 7 to 0:
[1] [2] [3]
If channels are run out-of-phase each will be staggered by one eighth of a PWM cycle. When more than one channel is selected by this command then the master signal is the channel with the lowest number. This does not apply to the external PWM signal on pin INP. Controls the point of the on-time at which the current is sampled for digital current measurement. Only operates when duty cycle is set to < 100 % or channel is mapped to pin INP. A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the default value if an SPI watchdog time-out occurs.
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The PWM frequency can be monitored by making this an output on pin PWMMON. This is a controller setting; see Section 9.5.5 "Controller settings".
9.3.5 Interrupt
An interrupt can be generated to notify a controller of an error condition. An interrupt will set pin INTN = LOW. Register settings define which faults can generate an interrupt and which FET channels can generate an interrupt for these faults.
Table 10. Address 24h Interrupt setting registers (addresses 24h, 28h) bit description Register IRQ_MAP[1] Bit Description interrupt request mapping; for each bit: 1 = INTN active 0 = INTN not active 7 6 5 4 3 2 1 0 28h IRQ_CHAN_MAP[1] 7 to 0 invalid SPI communication open-circuit controller fault (charge pump fault or VBAT low) temperature sensor diode open-circuit watchdog time-out channel overcurrent (threshold reached or exceeded) channel overtemperature (threshold exceeded) channel tripped under fault condition interrupt generation in individual channels 7 to 0: 1 = selected channel can generate interrupt 0 = selected channel cannot generate interrupt
[1] A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the default value if an SPI watchdog time-out occurs.
When an interrupt is generated, data in the interrupt status register will indicate the cause. See Section 11.1 "Reset for interrupt and SPI watchdog" for details of reading and clearing interrupt data.
9.4 Current measurement
The current measurement is able to monitor the current from the sense connections of the TrenchPLUS FETs. This is achieved by using one current measurement circuit for each channel. The current measurement circuits control conditions at the sense pin of each FET channel and can produce either an analog or digital measurement output. The digital output can be read by a controller. The current measurement circuit monitors the sense current according to the sense ratio of the TrenchPLUS FET. This ratio is only valid when the sense and main FETs of the TrenchPLUS device are fully active with VGS at about 4 V or greater, and with the same VGS.
9.4.1 Current measurement circuits
For FET channels configured as high-side switches, the sense current is pulled from the sense connection. This current is adjusted until the voltage measured at the FET pin kelvin is the same as that measured at the FET pin sense. Since the main and sense
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devices have common drain connections, the VDS of the two devices are equal, and the correct sense current is being pulled. Current measurement is only possible when the voltage on pin KELVIN is above the Vth(on)(bat-KEL) threshold.
9.4.2 Analog current measurement output
An analog current can be output on pin IMEAS that is proportional to the sense current measured on a selected FET channel. Any single channel can be multiplexed to this output at a time. The accuracy and resolution of analog current measurement is determined by the voltage across the RIMEAS resistor with the measurement output current and the measurement range used. The measurement current is given by Imeas = (ISENSE / Imeas(ADC)(fs)) x 100 A, where ISENSE is the FET sense current and Imeas(ADC)(fs) is the set full-scale current for the measurement range. For reliable current measurement, the voltage on pin IMEAS must be less than the measurement supply voltage on pin VCC(MEASC). A resistor value giving high resolution at low measurement output current (for example, up to Imeas(ADC)(fs)) may not provide the range for high measurement output current (for example, up to 8 x Imeas(ADC)(fs)). Conversely, a value giving the range for high measurement current will give less resolution for low measurement current. When the selected channel uses PWM, the analog measurement is able to follow the switched waveform, except when the duty cycle is very low, and high-side FETs are in the turn-on state. The voltage on pin IMEAS is limited just below the measurement supply voltage.
Table 11. Address 06h Analog current channel selection register (address 06h) bit description Register CURR_MEAS Bit 7 to 4 3 Description not used; must be set to logic 0 current measurement setting: 1 = enables current measurement in selected channel 0 = disables current measurement in all channels 2 to 0 selects measurement channel; binary value corresponds to channel number (0 to 7)
9.4.3 Digital current measurement output
8-bit successive approximation ADCs are used to measure the sense currents of the FET channels. The measured values are only considered valid when the FET has been on for the full conversion cycle. Digital measurements are stored and can be read by a controller. The reading from the ADC may not indicate zero if the channel is requested off. If PWM is not selected, the values are stored every ADC cycle. For PWM the digital measurement can be sampled at the start or end of the on time. The ADC reading, up to the maximum 255 bits, is given by: reading = 255 x (ISENSE / Imeas(ADC)(fs)) x (50 A / IIREFCURR), where IIREFCURR is the current through the current reference resistor (RIREFCURR). At IIREFCURR = 50 A this equation simplifies to give a direct relationship with the analog measurement current.
9.4.4 Low battery supply voltage conditions
The current measurement interface operates at voltages very near the battery voltage. To permit reasonable headroom in the circuit, the current measurement interface is powered from the charge pump. The circuit cannot operate correctly when it is close to ground, as
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occurs in very low battery conditions. The current measurement interface may be non-functional, or may have degraded accuracy under low (out-of-specification) charge pump conditions.
9.5 TrenchPLUS FET interface
The FET interface provides channel switching (on and off) and protection with the following features, described in priority order.
9.5.1 Overtemperature protection
Overtemperature protection is adjusted by selecting the trip level of the temperature sense diode for each channel. To relate this to actual trip temperature, refer to the specification of the specific TrenchPLUS FET devices. Overtemperature protection can also be set to auto-reset with hysteresis (to reduce the possibility of repeated resets when the temperature remains high) or to latch on fault. The device also detects and reports a fault if the connection to a temperature sense diode is open-circuit.
Table 12. Address 08h Overtemperature protection setting registers (addresses 08h, 18h, 19h) bit description Register Bit Description overtemperature fault clear in channels 3 to 0: 1 = selected channel set to auto reset with hysteresis 0 = selected channel set to latches on fault 18h OT_TRIPLEV_ CH30[1] set overtemperature trip level in channels 3 to 0 to one of four voltage trip levels[2]: 00 = 2.31 V 01 = 2.25 V 10 = 2.16 V 11 = 2.00 V 7, 6 5, 4 3, 2 1, 0 19h OT_TRIPLEV_ CH74[1] channel 3 temperature sense diode threshold voltage channel 2 temperature sense diode threshold voltage channel 1 temperature sense diode threshold voltage channel 0 temperature sense diode threshold voltage set overtemperature trip level in channels 7 to 4 to one of four voltage trip levels[2]: 00 = 2.31 V 01 = 2.25 V 10 = 2.16 V 11 = 2.00 V 7, 6 5, 4 3, 2 1, 0
[1] [2]
CHAN_OT_FAULT_ 7 to 0 CLR[1]
channel 7 temperature sense diode threshold voltage channel 6 temperature sense diode threshold voltage channel 5 temperature sense diode threshold voltage channel 4 temperature sense diode threshold voltage
A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the default value if an SPI watchdog time-out occurs. Nominal trip voltages quoted for each trip level. Refer to data sheet for TrenchPLUS FET devices for equivalent temperature measurement.
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9.5.2 Overcurrent protection
The overcurrent protection on each channel allows for high inrush currents. This protection also allows for turn-on or transient low battery conditions that can occur with the configuration of high-side FET switches. Delay time in operating overcurrent protection is determined by the actual FET. For high-side switches, FET turn-on is determined when the sense voltage exceeds the sense low threshold voltage (Vth(sense)low), within 40 s (nominal), and when the battery-to-kelvin voltage exceeds the on-state threshold voltage between the battery and pin KELVIN (Vth(on)(bat-KEL)). The following overcurrent protection is available: Turn-on overcurrent trip (TONOCH) -- For channels configured as high-side switches. Operates during FET turn-on or transient low battery conditions. The threshold level is a set multiple of Imeas(ADC)(fs) x (IIREFCURR / 50 A). This is simplified when IIREFCURR = 50 A. For low current sense voltage (< 2.5 V) the trip level is below the specified multiple of Imeas(ADC)(fs). This protection cannot be disabled. Overcurrent high trip (OCH) -- For channels configured as high-side switches. This does not operate during FET turn-on or transient low battery conditions. The threshold level is a set multiple of Imeas(ADC)(fs) x (IIREFCURR / 50 A). This is simplified when IIREFCURR = 50 A. This protection cannot be disabled or delayed. Overcurrent low trip (OCL) -- Operates at set currents of the ADC output up to Imeas(ADC)(fs) with the ADC measurement accuracy. The threshold level is set by register CURR_TRIPLEV_CHn. This protection can be disabled or delayed.
Table 13. Address 07h FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit description Register SEL_CURR_TRIP_CHAN[1] Bit Description 7 to 0 select current tripping for OCL in individual channels 7 to 0: 1 = selected 0 = not selected 1Ah IFSC_CH30[1] set Imeas(ADC)(fs) data bits in channels 3 to 0 to one of four current trip levels: 00 = 0.5 mA 01 = 1.0 mA 10 = 1.5 mA 11 = 2.0 mA 7, 6 5, 4 3, 2 1, 0 set channel 3 full-scale current bits 1 and 0 set channel 2 full-scale current bits 1 and 0 set channel 1 full-scale current bits 1 and 0 set channel 0 full-scale current bits 1 and 0
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FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit description ...continued Register IFSC_CH74[1] Bit Description set Imeas(ADC)(fs) data bits in channels 7 to 4 to one of four current trip levels: 00 = 0.5 mA 01 = 1.0 mA 10 = 1.5 mA 11 = 2.0 mA 7, 6 5, 4 3, 2 1, 0 set channel 7 full-scale current bits 1 and 0 set channel 6 full-scale current bits 1 and 0 set channel 5 full-scale current bits 1 and 0 set channel 4 full-scale current bits 1 and 0
Table 13. Address 1Bh
1Ch to 23h 25h
CURR_TRIPLEV_CHn[1] CURR_TRIP_BLANKTIME
7 to 0 overcurrent trip threshold in channels 7 to 0; each bit represents Imeas(ADC)(fs) / 255 7, 6 not used: must be set to logic 0 5 to 0 set overcurrent trip blanking time; see Table 14
[1]
A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the default value if an SPI watchdog time-out occurs.
Table 14. Blanking Value 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh
Overcurrent low trip blanking time Time 0 ms 0.08 ms 0.10 ms 0.11 ms 0.13 ms 0.16 ms 0.19 ms 0.22 ms 0.26 ms 0.32 ms 0.38 ms 0.45 ms Value 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h Time 0.51 ms 0.64 ms 0.77 ms 0.90 ms 1.0 ms 1.3 ms 1.5 ms 1.8 ms 2.0 ms 2.6 ms 3.1 ms 3.6 ms Value 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h Time 4.1 ms 5.1 ms 6.1 ms 7.2 ms 8.2 ms 10 ms 12 ms 14 ms 16 ms 20 ms 25 ms 29 ms Value 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh Time 33 ms 41 ms 49 ms 57 ms 66 ms 82 ms 98 ms 115 ms 131 ms 164 ms 197 ms 229 ms
9.5.3 Gate inductive ring-off clamp
For high-side switches an inductive ring-off clamp can provide gate-source voltage to allow conduction through the FET. This protects the FET by reducing the possibility of high drain-source voltages when turning off current to an inductive load. The gate is initially set to the source voltage to turn the FET off. During turn-off an inductive load will force the source voltage negative and the gate will follow this until the voltage between gate and ground reaches the inductive ring-off clamp voltage VCL. As the source voltage continues negative, the gate-to-source voltage will increase, turning the FET on and allowing conduction through the FET and preventing excessive voltage between drain and source.
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The negative voltage on the source then forces current in the inductive load to reduce rapidly to zero. As the source voltage returns to ground, the gate-source voltage becomes zero and the FET is turned off.
9.5.4 Loss-of-ground protection
A loss-of-ground condition can occur if the ground connection for the circuit is disconnected with the load ground still connected. With the FET off, it is possible for the ground voltage to drift up to battery voltage with the FET source voltage still held at ground. A resistance between pins GATE and KELVIN will hold the FET off provided the inductive ring-off clamp voltage VCL between gate and ground is not exceeded, otherwise the FET will start to turn on. Hence, loss of ground protection can only be guaranteed when VBAT < |VCL|.
9.5.5 Controller settings
It is possible to select a low switching rate for high-side switches at the beginning of turn-on and at the end of turn-off. This switching option improves EMC in the high-side switching application. The PWM frequency can be monitored on pin PWMMON. This output has a 50 % duty cycle.
Table 15. Address 0Eh Controller settings register (address 0Eh) bit description Register CTRL_SET[1] Bit 7 to 4 3 Description not applicable; set to logic 0 sets switching rate at start of turn-on and end of turn-off: 1 = low switching rate 0 = high switching rate 2 PWM signal on pin PWMMON: 1 = available 0 = not available[2] 1 to 0
[1] [2]
not used; must be set to logic 0
A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the default value if an SPI watchdog time-out occurs. When signal not available, this pin goes to 0 V.
9.5.6 Open-circuit detection
Open-circuit is normally detected when switches are in the on-state. The ADC checks that at least a minimal current is flowing through the sense circuit. The threshold level is determined by the setting DIG_OLTH[3:0] and is a mask option. For high-side switches it is possible to detect an open-circuit in the off-state. The FET kelvin source voltage is monitored with a current Idet(oc)off and an open-circuit is reported if the threshold voltage Vdet(oc)off is exceeded after a nominal 192 s delay. This off-state open-circuit detection is independent of on-state open-circuit detection. For high-side switches in the off-state, it is also possible to detect when the voltage between pin KELVIN and VBAT is less than Vth(on)(bat-KEL) (a short-circuit).
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Off-state open-circuit detection register (address 26h) bit description Bit Description 1 = off-state open-circuit detection enabled in selected channel 0 = off-state open-circuit detection disabled in selected channel OLDET_ONOFF 7 to 0 off-state open-circuit detection[1] in individual channels 7 to 0:
Table 16. 26h
Address Register
[1]
For high-side switches only.
9.5.7 Channel selection
Channel selection allows the FET channels to be switched on directly.
Table 17. Address 01h Channel selection register (address 01h) bit description Register CHAN_ONOFF Bit 7 to 0 Description direct switch-on of individual channels 7 to 0: 1 = selected channel on 0 = selected channel off
9.5.8 Mapping channels for direct channel control and PWM
Channels can be mapped to the input pin INP (intended for an external PWM signal) or to pins IN0 to IN3 for direct control (intended for fail-safe channel control by connection to VCC(LOG)EXT and GND, or an external PWM signal). All channels (0 to 7) can be mapped to pin INP. Channels 0 to 3 can be mapped to pins IN0 and IN1. Channels 4 to 7 can be mapped to pins IN2 and IN3. Input pins IN0 plus IN1 and IN2 plus IN3 are combined according to the AND/OR operation. If a channel is switched on (by register CHAN_ONOFF), the channel is switched on irrespective of the state on the direct input pins IN0 to IN3; see Section 9.5.7.
Table 18. Address 02h Channel selection and pin mapping register (addresses 02h to 05h) bit description Register IN02_MAP[1][2] Bit Description direct input pins IN0 and IN2 mapping: 1 = mapped 0 = not mapped 7 to 4 3 to 0 03h IN13_MAP[1][2] map individual channels 7 to 4 to pin IN2 map individual channels 3 to 0 to pin IN0 direct input pins IN1 and IN3 mapping: 1 = mapped 0 = not mapped 7 to 4 3 to 0 04h INP_MAP[2] 7 to 0 map individual channels 7 to 4 to pin IN3 map individual channels 3 to 0 to pin IN1 direct input pin INP map channels 7 to 0: 1 = mapped 0 = not mapped
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Channel selection and pin mapping register (addresses 02h to 05h) bit description ...continued Register ANDOR_MAP[1] 7 to 4 Bit Description direct input pin AND/OR operation direct input AND/OR operation for individual channels 7 to 4: 1 = pin IN2 AND pin IN3 0 = pin IN2 OR pin IN3 3 to 0 direct input AND/OR operation for individual channels 3 to 0: 1 = pin IN0 AND pin IN1 0 = pin IN0 OR pin IN1
Table 18. Address 05h
[1] [2]
A metal mask option WRITE_PROTECT is available, which means that these registers are reloaded with the default value if an SPI watchdog time-out occurs. In Watchdog mode; pins IN0 to IN3 reset channel faults (such as short-circuit) when the pin is set to LOW; Pin INP does not reset channel faults. Hence, it is not recommended that an external PWM signal is connected to pins IN0 to IN3 for normal operation.
9.5.9 FET channel on/off control
Each FET channel can be switched by a request from different sources, the logical relationship between these sources is shown in Figure 7.
watchdog timeout CHAN_ONOFFn IN02_MAPn IN0,IN2 IN13_MAPn IN1,IN3 1 0 0 1 ANDOR_MAPn INP_MAPn INP DIAG_DETAIL_CH0 ONn PWM_DC_CHn
CHAN_WD_MAPn
001aaf053
Fig 7. FET channel on/off request logic
9.5.10 Power dissipation
The FET interface comprises a significant part of the BUK3F00-50WD thermal budget. The dissipation is caused by the regulation of the SENSE pin voltage while sinking the sense current. The dissipation, per channel, can be estimated from the product of ISENSE and VBAT. Special care should be taken at high battery voltages that the power dissipation does not cause the device to overheat.
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9.5.11 Trip and retry
This automatically handles short duration OCH, TONOCH and OCL faults. However, switching into a short-circuit imposes considerable stress on the MOSFET and may reduce its life. The user must ensure that the effects are fully evaluated before implementation. If there is any doubt, then trip and retry should not be used. If trip and retry is used and a channel still trips off, then the channel should not be turned on again before the fault has been removed. This may require a lock-out feature in the controlling software. The settings for trip and retry are given in Table 19 "Protected settings".
9.5.12 Trip-latch
The faults listed will trip-latch a channel: this will not allow the channel to turn on unless the latch is cleared. Overtemperature -- with auto-reset turned off. Analog overcurrent -- with no retries allowed. Turn-on overcurrent HIGH -- (high-side switches only) with no retries allowed. Overcurrent LOW -- with no retries allowed and OCL tripping enabled. To clear a channel trip-latch condition; see Section 11.1 "Reset for interrupt and SPI watchdog".
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10. Fixed functional settings
A number of settings are fixed mask options. These settings do not have a register address and cannot be read or changed by the user.
Table 19. Name Protected settings Bit Description Version setting values FE DIG_OLTH open-circuit threshold level; 8-bit register 7 to 4 not applicable 3 to 0 high side: (0000) b3, b2, b1, b0 DIG_FET 8, 7 channel tripping behavior and filter times tlow(bat) setting: 00/11 = 128 s (min) to 144 s (max) 01 = 256 s (min) to 288 s (max) 10 = 512 s (min) to 576 s (max) 6, 5 thigh(bat) setting: 00/11 = 16 s (min) to 20 s (max) 01 = 32 s (min) to 40 s (max) 10 = 64 s (min) to 80 s (max) 4 high-side channels on low VBAT: 1 = no trip 0 = trip 3, 2 1, 0 trip channel output filter time: 00 = immediate TONOCH filter time (in turn-on state): 00 = immediate 01 = 1.0 s 10 = 1.5 s 11 = 2.0 s (min) to 3.0 s (max) CHAN_ALLOW_RETRY 7 to 0 allow trip and retry after OCH, TONOCH or OCL faults select channels 7 to 0: 1 = allowed 0 = not allowed RETRY_SETTINGS 4, 3 trip retry delay and number of retries wait time before retry: 00 = 64 s (min) to 128 s (max) 01 = 192 s (min) to 256 s (max) 10 = 320 s (min) to 384 s (max) 11 = 448 s (min) to 512 s (max) 2 to 0 number of retries, set binary number WRITE_PROTECT 0 write protect (registers WD_TO and CHAN_WD_MAP)[1]: 1 = no write access 0 = write access 1b 1b 1b 1Bh 1Bh 1Bh FFh FFh FFh 0C1h 0C1h 0C1h 23h FM 23h FY 23h
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Table 19. Name
Protected settings ...continued Bit Description Version setting values FE FM 00h FY 00h
WDPN_LOW_TIME
7 to 0 watchdog time-out LOW time pulse (on pin WDTON) 00h = 1.0 ms 01h = 1.3 ms 02h = 1.5 ms 03h = 1.8 ms 04h = 2.0 ms 05h = 2.6 ms 06h = 3.1 ms 07h = 3.6 ms 08h = 4.1 ms 09h = 5.1 ms 0Ah = 6.1 ms 0Bh = 7.2 ms 0Ch = 8.2 ms 0Dh = 10 ms 0Eh = 12 ms 0Fh = 14 ms 10h = 16 ms 11h = 20 ms 12h = 25 ms 13h = 29 ms 14h = 33 ms 15h = 41 ms 16h = 49 ms 17h = 57 ms 18h = 66 ms 19h = 82 ms 1Ah = 98 ms 1Bh = 115 ms 1Ch = 131 ms 1Dh = 164 ms 1Eh = 197 ms 1Fh = 229 ms
00h
VSBATLOW_DEB_EN
0
debounce on VBAT low signal: 1 = debounce enabled 0 = debounce disabled
0b
0b
0b
NXIFSC_CH0 NXIFSC_CH1 NXIFSC_CH2 NXIFSC_CH3 NXIFSC_CH4 NXIFSC_CH5 NXIFSC_CH6 NXIFSC_CH7 HL_CH0 to HL_CH7 FIXED_GATE_SLEW_RATE
-
channel 0: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 1: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 2: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 3: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 4: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 5: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 6: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 7: ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 0 to 7: FET configuration (high or low side) rising and falling slew rates have fixed values during gate turn-on
6 6 6 6 3 6 6 6 high no
6 6 6 6 6 6 6 6 high yes
6 6 6 6 6 6 6 6 high yes
[1]
Also sets default register reload for watchdog time-out.
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11. Diagnostic functions
11.1 Reset for interrupt and SPI watchdog
An interrupt or SPI watchdog time-out can be reset by writing to the relevant write-only register. Values are not stored and cannot be read back.
Table 20. Address 29h Write-only (for reset) registers (addresses 29h, 2Ah) bit description Register Bit Description writing any value other than 00h to this register clears the interrupt and ISR register writing a logic 1 to any bit in this register clears the interrupt and ISR register AND clears the trip latch (resetting the retry register) for that specific channel 2Ah CLEAR_WD 7 to 0 clear watchdog state: writing any value to this register clears SPI Watchdog mode CLEAR_CHAN_INTN 7 to 0 clears all channels (7 to 0) and interrupt:
11.2 Diagnostic data
Diagnostic data can be obtained by reading data from the relevant 16-bit read-only registers. Send the register address as data to register READBACK (27h).
Table 21. Address 30h Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description Register DIAG_BASIC 15, 14 13, 12 11, 10 9, 8 7, 6 5, 4 3, 2 1, 0 31h DIAG_CTRL 15 14 13 12 11 10 9 8 7 to 0 Bit Description basic diagnostics channel 7 basic diagnostics channel 6 basic diagnostics channel 5 basic diagnostics channel 4 basic diagnostics channel 3 basic diagnostics channel 2 basic diagnostics channel 1 basic diagnostics channel 0 basic diagnostics controller diagnostics SPI error: wrong number of bits VBAT low SPI error: invalid address charge pump fault not used logic reset has occurred watchdog time-out has occurred watchdog is enabled channel configuration: 1 = high side 0 = low side
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Bit latches
[1]
yes[2] yes[3][4] yes[2] yes[3][4] yes[3] yes[3]
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Controller for TrenchPLUS FETs
Table 21. Address 32h
Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description ...continued Register ISR 15 14 13 12 11 10 9 8 7 to 5 4 3 2 1 0 Bit Description interrupt status channel overtemperature logic reset has occurred channel tripped by controller (low battery) VBAT too low charge pump fault watchdog time-out wrong number of bits in SPI communication invalid address in SPI communication channel index generating interrupt (binary number) channel tripped by overcurrent channel tripped by overtemperature channel overcurrent channel open-circuit channel temperature sensor diode open-circuit device version number 15 to 8 7 to 0 main version sub-version code high-side FET on-state and open-circuit detection 15 to 8 7 to 0 high-side FET in on-state for channels 7 to 0 high-side FET open-circuit detected on channels 7 to 0 TSNSOPEN and overtemperature detection states 15 to 8 7 to 0 value of TSNSOPEN signal for channels 7 to 0 not used detail diagnostics channels 7 to 0 15 to 8 7 6 5 4 3 2 1 0 digital current measurement channel temperature sensor open-circuit open-circuit load detected not used channel overcurrent channel overtemperature channel tripped by controller (low battery) shorted output to VBAT channel requested by user
[13] [16] [17] [18] [5] [6][7] [8] [8][12] [8] [8] [9] [10] [10] [6] [6][11][12] [6][7] [6][11][13] [6][14] [6][15]
Bit latches yes yes yes yes yes yes yes yes yes yes yes yes yes yes
33h
VERSION
34h
DIAG_CHAN_01
35h
DIAG_CHAN_02
38h to 3Fh
DIAG_DETAIL_CHn
yes[18] yes[18] yes[18] yes[18] yes[18] yes[18]
[1]
Values for each channel are (in priority order): 00 = no controller fault. 10 = channel selected (normal or PWM). Applies during the PWM period when the channel and PWM are both selected. 01 = channel not selected but controller fault (low battery). This is latched, only cleared by reading DIAG_CTRL or selecting channel. 11 = channel selected but tripped off. Applies when the channel is selected but tripped by overcurrent or overtemperature. Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided SPI fault is mapped to INTN). Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided controller fault is mapped to INTN).
(c) NXP B.V. 2008. All rights reserved.
[2] [3]
BUK3F00-50WDXX_2
Product data sheet
Rev. 02 -- 21 January 2008
28 of 51
NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
[4] [5] [6] [7] [8] [9]
When bit is cleared, value 01 in DIAG_BASIC is also cleared. The bits in this register latch when an interrupt is generated by the given source, once captured no new data is latched. The register is cleared by writing to CLEAR_CHAN_INTN. Requires specific channel mapped in IRQ_CHAN_MAP. Requires channel overtemperature to be mapped in IRQ_MAP. Requires controller fault to be mapped in IRQ_MAP. Requires watchdog time-out to be mapped in IRQ_MAP.
[10] Requires SPI error to be mapped in IRQ_MAP. [11] Requires channel overcurrent to be mapped in IRQ_MAP. [12] Mapping channel tripped in IRQ_MAP also enables this bit. [13] If OCL protection is disabled and current exceeds the OCL level, the register bit is still set and an interrupt generated (provided channel overcurrent is mapped in IRQ_MAP). This is also true if OCL is delayed and the current exceeds the OCL level during the delay period. [14] Requires open-circuit detected to be mapped in IRQ_MAP. [15] Requires temperature sensor diode open-circuit to be mapped in IRQ_MAP. [16] Denotes main product version: 50WDFE: 0Ah Other types: 0Bh [17] Denotes type or mask version: 50WDFE: 02 50WDFM: 01 50WDFY: 02 Versions may change if mask changes occur during production. [18] Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN.
BUK3F00-50WDXX_2
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Product data sheet
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
12. Application design-in information
VBAT
Crf Cflt(CP) Cstg Rflt(CP) Cflt(CP)
VOLTAGE REGULATOR
Cmod
Cp
VBAT(CP)
supply
Rflt
VCC(MOD) VCC(DIGC)
Cflt
VBAT ANODE GATE
Cgate(comp)
CPN
CPP
CT
TrenchPLUS FET (8x)
VCC(LOG)EXT SENSE
RINTN RWDTON
KELVIN
ENABLE TIMEOUT MICROCONTROLLER RESET INTERRUPT
WDEN WDTON EN INTN
BUK3F0050WDxx
RL
Crf
serial periheral interface
ENABLE CLOCK DATA OUT DATA IN
SCSN SCLK SDI SDO PWMMON
IREFCURR IREFTEMP
RIREFTEMP
RIREFCURR
A/D
SUPPLY MEASURE
VCC(MEASC) IMEAS GND(DIGC) GND(CP) GND
ground
RIMEAS
ensure potential between grounds < 0.5 V
001aaf240
Fig 8. Application schematic
The charge pump pin VBAT(CP) can be connected in any one of the following ways:
* Connected directly to pin VBAT and the battery supply. * Connected through the internal resistor to pin VBAT and the battery supply. * Connected through the internal resistor to pin VBAT and a filter circuit to the battery
supply (as shown). The method used depends on how important reducing the effect of charge pump noise is for the application circuit.
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Product data sheet
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Table 22.
External component requirements Value 20 nF (min) 1 F (min)
[1] [2]
Component Remark Charge pump capacitors Cp Cstg RIREFTEMP RIREFCURR RIMEAS non-electrolytic; connect between pins CPP and CPN non-electrolytic; connect between pins VBAT(CP) and CT connect between pins IREFTEMP and GND connect between pins IREFCURR and GND connect between pins IMEAS and GND for sense currents up to 3 x Imeas(ADC)(fs) for sense currents up to 8 x Imeas(ADC)(fs) Digital output pull-up resistors RINTN RWDTON Rsense connect between pins INTN and VCC(LOG)EXT connect between pins WDTON and VCC(LOG)EXT
[4] [3] [3]
Current reference and measurement resistors 24.9 k 1 % 24.9 k 1 % 10 k 2 % 4.7 k 2 % 3.3 k (min); 10 k (typ); 100 k (max) 3.3 k (min); 10 k (typ); 100 k (max) 100 (min); 700 (max) 50 (min); 350 (max) 33.3 (min); 233.3 (max) 25 (min); 125 (max) 100 F 20 %
[5] [5]
TrenchPLUS FET sense resistance Imeas(ADC)(fs) = 0.5 mA Imeas(ADC)(fs) = 1.0 mA Imeas(ADC)(fs) = 1.5 mA Imeas(ADC)(fs) = 2.0 mA Module supply decoupling Cmod Rflt Cflt electrolytic connect between pins VCC(MOD) plus VCC(DIGC) and supply non-electrolytic; connect between pins VCC(MOD) plus VCC(DIGC) and GND charge pump filter resistor connect between pin VBAT and battery supply charge pump filter capacitors connect between pin VBAT and GND and between Rflt(CP) and GND for FETs with low Ciss value to be determined in the application circuit value to be determined in the application circuit connect between pins VCC(LOG)EXT, VCC(MOD) and pins IN0 to IN3 as required.
10 2 % 100 nF 5 %
Optional charge pump filtering Rflt(CP) Cflt(CP)
[6]
20 (max) 100 nF (max)
Optional gate Ciss compensation Cgate(comp) Crf Load resistor RL RINP 50 k 2 % Direct input pin resistors (not shown) 1 nF 5 % Application circuit decoupling
[1] [2] [3] [4] [5]
Sets IF to nominal 250 A. Sets IIREFCURR to nominal 50 A. Selection of RIMEAS for sufficient dynamic range is also dependant on voltage of VCC(MEASC). Values quoted assume VCC(MEASC) = 5 V. Rsense is the drain-source resistance of the sense cells of the TrenchPLUS FET at the nominal drain current. It can be estimated from the product of the current-sense ratio and the drain-source resistance of the main FET. Pins VCC(MOD) and VCC(DIGC) can each have separate filtering for good decoupling.
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Product data sheet
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
[6]
If Rflt(CP) is not connected, then connect VBAT directly with a short. If required, the charge pump can also be supplied directly from VBAT.
Table 23. Gate Drain Source Kelvin Sense Anode Cathode
TrenchPLUS FET connections per channel Description gate of the output power MOSFET switch drain of the output power MOSFET switch source of the output power MOSFET switch kelvin source connection for current measurement analog current measurement cell of the MOSFET switch (provides input for digital and analog current measurement) temperature sense diode (electrically isolated from other connections) temperature sense diode (electrically isolated from other connections); connect to GND
Connection
13. Limiting values
Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Ptot Tj Tstg Power supplies VBAT VCC(MOD) VBAT(CP) VCC(DIGC) VCC(LOG)EXT VCC(MEASC) battery supply voltage module supply voltage charge pump battery supply voltage digital core supply voltage external logic supply voltage measure circuit supply voltage
[4] [3] [2]
Parameter total power dissipation junction temperature storage temperature
Conditions Tamb 85 C
[1]
Min -40 -40 -32 -0.5 -32 -0.5 -0.5 -0.5 -0.5
Max 1 +150 +150 +60 +60 +60 +60 +5.5 +7 +0.5
Unit W C C V V V V V V V
VVBAT-VBAT(CP) voltage difference between pin VBAT and pin VBAT(CP) Ground levels[5] VGND(bat-cp) VGND(bat-log) VGND(cp-log) ground voltage difference from battery to charge pump ground voltage difference from battery to logic ground voltage difference from charge pump to logic voltage on pin x voltage difference GND to GND(CP) GND to GND(DIGC) GND(CP) to GND(DIGC)
-0.5 -0.5 -0.5
+0.5 +0.5 +0.5
V V V
FET connection pins Vx V pins GATE, KELVIN, SENSE pin ANODE between pins KELVIN and VBAT between KELVIN pins of 2 channels and between SENSE pins of 2 channels VI(cm)
BUK3F00-50WDXX_2
-32 -0.5 -60 -60
+60 +7 +2 +60
V V V V
common-mode input voltage
pins KELVIN and SENSE (for sense current measurement)
Rev. 02 -- 21 January 2008
-40
VBAT + 1 V
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Controller for TrenchPLUS FETs
Table 24. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VI(dig) II(dig) VESD Parameter digital input voltage digital input current electrostatic discharge voltage CDM corner pins other pins HBM
[1] [2] [3] [4] [5] [6] [7]
[7] [6]
Conditions pins EN, IN0, IN1, IN2, IN3, INP, SCLK, SCSN, SDI, WDEN
Min -1.5 -
Max 1
Unit V mA
Digital input pins
Electrostatic discharge voltages 750 500 2 V V kV
When Tj > 125 C, the device will function, but electrical parameters may deviate from the specified values. Circuits will survive higher transient voltages, provided the clamp rating is not exceeded. This limiting value also applies to the open-drain output pins INTN and WDTON. Pin VBAT can be connected from battery supply through pin VBAT(CP) and internal resistor. All 4 GND pins must be connected together to ground. CDM: C = 200 pF according to AEC-Q100-002 and 011. HBM: C = 100 pF; R = 1.5 k according to AEC-Q100-002 and 011.
14. Recommended operating conditions
Table 25. Symbol Supplies VBAT VBAT(CP) VCC(MOD) VCC(DIGC) VCC(MEASC) SRbat General Tamb VI(cm) ambient temperature common-mode input voltage pins KELVIN and SENSE (for sense current measurement) on pin INP on pins IN0, IN1, IN2 and IN3 -40 VBAT - 2.5 0 10 10 +25 +125 VBAT + 0.3 512 512 3 C V FET connection pins battery supply voltage charge pump battery supply voltage module supply voltage digital core supply voltage measure circuit supply voltage battery slew rate
[2]
Recommended operating conditions Parameter Conditions operating
[1]
Min 5.5 9 4.6 4.6 3.3 3.3 -
Typ 13 13 13 13 5 5 -
Max 52 52 52 52 5.5 5.5 100
Unit V V V V V V V/s
VCC(LOG)EXT external logic supply voltage
Direct input pins fPWM(ext) fsw fSPI tsu(SCSN) td(SCSN)
BUK3F00-50WDXX_2
external PWM frequency switching frequency
[3]
-
Hz Hz MHz ns ns
SPI timing; see Figure 9
SPI frequency SCSN set-up time SCSN delay time
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Table 25. Symbol tw(SCSN) tsu(SDI) th(SDI) tSCLKH tSCLKL
[1] [2] [3]
Recommended operating conditions ...continued Parameter SCSN pulse width SDI set-up time SDI hold time SCLK HIGH time SCLK LOW time Conditions Min 2 10 10 50 50 Typ Max Unit s ns ns ns ns
When VBAT < 9 V, the charge pump cannot be guaranteed to drive the external MOSFETs to achieve their specified RDSon. Higher slew rates can give uncontrolled device turn-on, device turn-off or channel switching. For SDO output characteristics; see Table 30 "SPI and watchdog characteristics".
tw(SCSN) SCSN tsu(SCSN) SCLK th(SDI) SDI tv(SDO) SDO
001aaf463
tsu(SDI)
tSCLKH
tdis(SDO)
tSCLKL
td(SCSN)
th(SDO)
The shaded areas indicate the time that output data is not valid.
Fig 9. SPI timing definitions
15. Thermal characteristics
Table 26. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions mounted on single-layer PCB, size 11.43 cm x 7.62 cm (4.5 inch x 3.0 inch) in free air at 1 m/s at 2.5 m/s Rth(j-pcb) Rth(j-c) thermal resistance from junction to printed-circuit board thermal resistance from junction to case board cooled by cold plate case cooled at constant temperature 66 54 50 23 35 K/W K/W K/W K/W K/W Typ Unit
BUK3F00-50WDXX_2
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Controller for TrenchPLUS FETs
16. Characteristics
Table 27. Supplies characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies: pins VBAT, VBAT(CP), VCC(MOD), VCC(LOG)EXT and VCC(MEASC) Standby and quiescent currents (pin EN = LOW) Istb(bat) Istb(mod) Iq(log)ext Iq(meas) battery standby current module standby current external logic quiescent current measure quiescent current VBAT = VBAT(CP) = 52 V VCC(MOD) = VCC(DIGC) = 52 V VCC(LOG)EXT = 5 V; pins SCSN and WDEN not connected VCC(MEASC) = 5 V
[1][2] [3][2] [4]
-
1.25 5 6.75 15 1 1
A A A A
Operating currents (pin EN = HIGH) Ioper(bat) Ibat(M) Ioper(mod) Imod(M) Ilog(ext)M Ioper(meas) battery operating current VBAT = VBAT(CP) = 13 V; ISENSE = 2 mA [Imeas(ADC)(fs)] peak battery current VBAT = VBAT(CP) = 40 V; ISENSE = 6 x 2 mA [Imeas(ADC)(fs)]
[1][5]
3 5 -
-
10 12.5 10 12.5 450 1.5 x IO(meas) + 30 80
mA mA mA mA A A
[1][5]
module operating current VCC(MOD) = VCC(DIGC) = 13 V; ISENSE = 2 mA [Imeas(ADC)(fs)] peak module current peak external logic current measure operating current clamping voltage VCC(MOD) = VCC(DIGC) = 40 V; ISENSE = 6 x 2 mA [Imeas(ADC)(fs)] VCC(LOG)EXT = 5 V; pin WDEN = LOW; pin SDO at 3 MHz; CL = 20 pF VCC(MEASC) = 5 V; RIREFCURR = RIREFTEMP = 24.9 k ICL = 10 mA; tp = 300 s
[3][5]
[3][5]
[4]
Transient voltages: pins VBAT, VCC(MOD), VCC(LOG)EXT, VBAT(CP), CPP, CPN, CT, GATE, KELVIN, SENSE VCL 67.5 V Battery supply: pin VBAT and VBAT(CP) Normal battery operation Vth(uv)bat Vhys(uv)bat Vth(low)bat Vhys(low)bat battery undervoltage threshold voltage battery undervoltage hysteresis voltage battery low threshold voltage battery low hysteresis voltage voltage from gate to battery battery reverse current module undervoltage threshold voltage VBAT = -4 V VBAT = -30 V VBAT = VBAT(CP) = -30 V HIGH-to-LOW LOW-to-HIGH
[1]
HIGH-to-LOW LOW-to-HIGH
[6]
4.7 140
200
5.2 5.4 250 2.15 2.4 300
V V mV V V mV
4.95 [6]
HIGH-to-LOW LOW-to-HIGH
[6] [6] [6]
1.85 2.1 150 225
Reverse battery operation VG-bat IR(bat) Vth(uv)mod 8 4.1 4.2 3.0 11 10 4.55 4.6 V V mA V V
Module supply: pin VCC(MOD)
BUK3F00-50WDXX_2
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Product data sheet
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NXP Semiconductors
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Controller for TrenchPLUS FETs
Table 27. Supplies characteristics ...continued VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol Parameter Conditions Min 25 Typ 50 Max 130 Unit mV Vhys(uv)mod module undervoltage hysteresis voltage Reference outputs: pins IREFTEMP and IREFCURR VO(ref) IO(ref)
[1] [2] [3] [4] [5] [6]
reference output voltage reference output current
RIREFCURR = RIREFTEMP = 24.9 k
1.20 1.24 1.28 49.8 -
V A
Total current = IBAT + IBAT(CP). Standby currents valid provided VBAT and VCC(MOD) > 9 V. Total current = ICC(MOD) + ICC(DIGC). Does not include current through pins INTN or WDTON pull-up resistors. All channels ON; with FET Crss = 210 pF; fSPI = 3 MHz. Monitored on pin VBAT(CP).
Table 28. Charge pump characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol fosc(cp) VO(cp) tbst(cp) Vth(fault)cp Vhys(fault)cp Parameter Conditions Min 400 4.5 6 2.6 50 Typ 500 6.5 500 150 Max 600 7.5 3 250 Unit kHz V V s V V mV Charge pump: pins VBAT(CP), CPP, CPN and CT charge pump oscillator frequency VBAT > 5.5 V charge pump output voltage charge pump boost time charge pump fault threshold voltage charge pump fault hysteresis voltage VBAT = 5.5 V to 9 V VBAT > 9 V Cstg = 1 F; VBAT > 5.5 V HIGH-to-LOW LOW-to-HIGH
Table 29. Control circuits characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol VIL VIH Vhys(I) VCL(i) Cin Rpd ten tdis VOL
BUK3F00-50WDXX_2
Parameter LOW-level input voltage HIGH-level input voltage input hysteresis voltage input clamping voltage input capacitance pull-down resistance enable time disable time LOW-level output voltage
Conditions
Min 1 150 9.5 50
[1]
Typ 10.5 10 100 1 -
Max 2 550 11.5 250 100 1.6 0.4
Unit V V mV V pF k s ms V
Digital control input: pin EN
-
Interrupt output: pin INTN II = 1.6 mA -
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 21 January 2008
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Table 29. Control circuits characteristics ...continued VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol VIL VIH Vhys(I) Cin Rpd
[1]
Parameter LOW-level input voltage HIGH-level input voltage input hysteresis voltage input capacitance pull-down resistance
Conditions
Min 1 200 50
Typ 10 100
Max 2 700 250
Unit V V mV pF k
Direct channel control inputs: pins IN0, IN1, IN2 and IN3
The time when both analog and digital circuits are enabled. High-side channels cannot be switched until the charge pump boost time has also elapsed.
Table 30. SPI and watchdog characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol VIL VIH Vhys(I) Cin VOL VOH(log)(ext) Rpd Rpu th(SDO) tv(SDO) tdis(SDO) VIL VIH Vhys(I) VCL(i) Cin Rpu VOL tto(wd)/tto(wd) Parameter LOW-level input voltage HIGH-level input voltage input hysteresis voltage input capacitance LOW-level output voltage external logic HIGH-level output voltage pull-down resistance pull-up resistance SDO hold time SDO valid time SDO disable time LOW-level input voltage HIGH-level input voltage input hysteresis voltage input clamping voltage input capacitance pull-up resistance LOW-level output voltage relative watchdog time-out time variation pin WDEN IO = 1.6 mA pin WDEN = HIGH
[1]
Conditions
Min 1 200 -
Typ 10 100 100 10.5 10 100 -
Max 2 700 0.4 250 250 100 116 100 2 700 11.5 250 0.4 28
Unit V V mV pF V V k k ns ns ns V V mV V pF k V %
SPI input pins SCSN, SCLK, SDI and output pin SDO
II = 1.6 mA IO = 1 mA pins SCLK and SDI pin SCSN CL = 200 pF
VCC(LOG)EXT - 0.4 50 50 1 200 9.5 50 0
Watchdog input pin WDEN and output pin WDTON
[1]
Relative watchdog time-out time variation does not include clock frequency variation.
BUK3F00-50WDXX_2
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Product data sheet
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NXP Semiconductors
BUK3F00-50WDXX
Controller for TrenchPLUS FETs
Table 31. Pulse-width modulation characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol fPWM/fPWM VIL VIH Vhys(I) VCL(i) Cin Rpd VOL VOH(log)(ext) Parameter relative PWM frequency variation LOW-level input voltage HIGH-level input voltage input hysteresis voltage input clamping voltage input capacitance pull-down resistance LOW-level output voltage external logic HIGH-level output voltage II = 1.6 mA IO = 1 mA Conditions
[1]
Min -20 1 200 9.5 50 VCC(LOG)EXT - 0.4
Typ 10.5 10 100 -
Max +20 2 700 11.5 250 0.4 -
Unit % V V mV V pF k V V
Pulse-width modulator PWM input: pin INP
PWM output: pin PWMMON
[1]
Relative PWM frequency error includes clock frequency variation.
Table 32. Current measurement characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol Parameter Current EADC(I) measurement[1] ADC error (current) all ranges; RIREFCURR = 24.9 k 0.01 x Imeas(ADC)(fs) 0.20 x Imeas(ADC)(fs) 0.80 x Imeas(ADC)(fs) type 50WDFE other 50WDxx types IO(meas) measure output current all ranges; VCC(MEASC) = 5 V; RIMEAS = 4.7 k; RIREFCURR = 24.9 k 0.00 x Imeas(ADC)(fs) 0.20 x Imeas(ADC)(fs) 1.00 x Imeas(ADC)(fs) 8.00 x Imeas(ADC)(fs)
[1] [2] [3]
[2] [3]
Conditions
Min
Typ
Max
Unit
-2 -4 -11 -13
-
+2 +4 +15 +13
bit bit bit bit
15 92.5 660
0 20 102.5 820
5 25 112.5 980
A A A A
If measured without a FET, then connect a suitable resistor between pins VBAT and SENSE to ensure stability. ADC accuracy ensured when VBAT and VCC(MOD) > 9 V. ADC used at this level for on-state open-circuit detection.
BUK3F00-50WDXX_2
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Product data sheet
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Controller for TrenchPLUS FETs
Table 33. Gate drive high-side switches characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol VGS Parameter gate-source voltage Conditions on-state VBAT = 5.5 V to 9 V VBAT > 9 V VCL(G) SRr gate clamping voltage rising slew rate inductive ring-off CTRL_SET[3] = 0 OR VKELVIN-GND > 2.5 V (high region); FET Crss = 210 pF CTRL_SET[3] = 1 AND VKELVIN-GND < 2.5 V (low region); FET Crss = 210 pF SRf falling slew rate CTRL_SET[3] = 0 OR VKELVIN-GND > 2.5 V (high region); FET Crss = 210 pF CTRL_SET[3] = 1 AND VKELVIN-GND < 2.5 V (low region); FET Crss = 210 pF Ro(GATE-KELVIN) output resistance between pin GATE and pin KELVIN Standby mode; pin EN = LOW gate hold-off loss of ground; pin GND = VBAT IG(sc)
[1] [2]
[2] [2] [1] [1]
Min
Typ
Max Unit
Gate drive for high-side switches 4.0 5.5 0.5 0.25 0.5 0.25 70 70 30 6.5 1 0.5 1 0.5 130 130 80 7.5 7.5 1.2 0.6 1.2 0.6 230 230 190 2.5 V V V V/s V/s V/s V/s k mA
-28.5 -22.5 -20
short-circuit gate current
channel on; short-circuit to ground
If fixed gate slew rate option is set, then rising and falling slew rates are constant irrespective of VKELVIN-GND. For accurate measurement of slew rates, VBAT supply must remain constant during test. Specification includes pin KELVIN series resistance.
Table 34. Protection circuits characteristics VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol IF Vtrip(otp) Parameter forward current over-temperature protection trip voltage Conditions RIREFTEMP = 24.9 k RIREFTEMP = 24.9 k trip level setting = 00b trip level setting = 01b trip level setting = 10b trip level setting = 11b Vhys(trip)otp over-temperature protection trip hysteresis voltage trip filter time temperature sensor diode open-circuit detection threshold voltage Tamb = -40 C Tamb = +125 C
[1]
Min 236 2.255 2.198 2.108 1.953 40
Typ 248 2.305 2.248 2.158 2.003 50
Max 260 2.348 2.291 2.201 2.046 60
Unit A V V V V mV
Overtemperature protection
tfltr(trip) Vth(det)oc(TSD)
26 2.5 2.4
-
57 3.9 3.8
s V V
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Product data sheet
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Table 34. Protection circuits characteristics ...continued VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 C; limit values are given at Tcase = -40 C to +125 C; unless otherwise specified. Symbol Overcurrent Vth(on)(bat-KEL) Parameter protection[2] on-state threshold voltage between battery and pin KELVIN HIGH-to-LOW LOW-to-HIGH
[3]
Conditions
Min 1.65 1.50 -
Typ 1.95 1.80 150
Max 2.25 2.10 -
Unit V V mV
Vhys(on)(bat-KEL) on-state hysteresis voltage from battery to pin KELVIN Itrip/Itrip relative trip current variation OCH; RIREFCURR = 24.9 k TONOCH; RIREFCURR = 24.9 k; high-side switch in turn-on state; VSENSE = 2.5 V trip ratio 5 trip ratio 4 tblank/tblank Vth(sense)low relative blanking time variation low sense threshold voltage on-state open-circuit detection current HIGH-to-LOW; TONOCH operation DIG_OLTH[3:0] = 3; RIREFCURR = 24.9 k; all ranges open-circuit not detected open-circuit detected Idet(oc)off off-state open-circuit detection current VKELVIN = 2.5 V type 50WDFE other 50WDxx types Vdet(oc)off off-state open-circuit detection voltage
[6] [3][4] [4][5]
-7.5
+3
+15
%
-10 -7.5 0 1
+5 +7.5 1.25
+20 +22.5 28 1.5
% % % V
Open-circuit detection Idet(oc)on
4.5 / 255 x Imeas(ADC)(fs) 40 55 2.4
-
0.5 / 255 x Imeas(ADC)(fs) -
A A
2.6
100 115 2.8
A A V
[1] [2] [3] [4] [5] [6]
Nominal trip voltages quoted for each level. Refer to data sheet for TrenchPLUS FET devices for equivalent temperature measurement. If measured without a FET, then connect a suitable resistor between pins VBAT and SENSE to ensure stability. Accuracy ensured when VBAT and VCC(MOD) > 9 V. Nominal Itrip = n x Imeas(ADC)(fs), where n is the OCH and TONOCH trip level ratio for the product type; see NXIFSC_CHn in Table 19. Until the channel is fully turned on, when voltage from battery to pin KELVIN < Vth(on)(bat-KEL). Relative blanking time variation does not include clock frequency variation.
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17. Application information
17.1 ElectroMagnetic Compatibility guidelines
In some applications, problems associated with electromagnetic interference can occur, such as false overcurrent tripping, false overtemperature tripping or unexpected turn-on of individual channels. Vulnerable points can be where currents are induced from wiring harness connectors positioned close to sensitive control tracks (such as control lines or FET gate, sense and kelvin lines). Good PCB and circuit design, following RF design principles, can ensure such problems are avoided. The following guidelines are provided to achieve this.
17.1.1 Ground layers
In multilayer PCB design, keep sensitive analog signals on the top PCB layer with a second ground layer acting as a shield. There should be no slits or breaks in this ground layer.
17.1.2 Circuit loops and tracks
Keep the area of circuit loops small and the length of sensitive tracks short with components positioned as closely as possible. This particularly applies to FET gate, sense and kelvin lines.
17.1.3 Connector decoupling
Decoupling capacitors should be fitted directly on, or as close as possible to, connectors, preventing currents being induced on FET or control tracks.
17.1.4 Module supply decoupling
This supply can be decoupled for EMC with a small ferrite bead. Circuit analysis should include assessment of possible paths for EMC-induced currents from different wiring harnesses connected to the PCB.
17.2 ADC accuracy
The ADC accuracy can be calculated at different measurement points using the graphs Figure 10 and Figure 11 or associated equation. The effect of additional errors in the reference current resistor can be estimated as a proportion of the resistor value.
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25 absolute bit error 20 y = 10.4x2 + 7.9x + 2 15
001aag055
10
5
0 0 20 40 60 80 100 ADC measurement (% full scale)
RIREFCURR = 24.9 k.
Fig 10. Maximum ADC bit errors (type 50WDFE)
20 absolute bit error 16 y = 5.5x2 + 9.7x + 2 12
001aaf455
8
4
0 0 20 40 60 80 100 ADC measurement (% full scale)
RIREFCURR = 24.9 k.
Fig 11. Maximum ADC bit errors (other 50WDxx types)
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17.3 Additional metal mask options
Additional metal mask options can be provided with different default settings. Table 35 can be used to submit these requirements for assessment.
Table 35. 02h 03h 04h 05h 07h 08h 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 24h 25h Registers for mask options Description direct input pins IN0 and IN2 mapping direct input pins IN1 and IN3 mapping PWM input pin INP mapping direct input pin AND/OR operation select current tripping channel channel set overtemperature fault clear select channel watchdog behavior watchdog time-out period setting controller settings internal PWM frequency setting internal PWM duty cycle setting for channel 0 internal PWM duty cycle setting for channel 1 internal PWM duty cycle setting for channel 2 internal PWM duty cycle setting for channel 3 internal PWM duty cycle setting for channel 4 internal PWM duty cycle setting for channel 5 internal PWM duty cycle setting for channel 6 internal PWM duty cycle setting for channel 7 overtemperature trip level channels 3 to 0 overtemperature trip level channels 7 to 4 full-scale reference current channels 3 to 0 full-scale reference current channels 7 to 4 interrupt request mapping current trip blanking time open-circuit threshold level channel tripping behavior and filter times channel allow trip and retry after OCH or TONOCH faults trip retry delay and number of retries write protect (registers WD_TO and CHAN_WD_MAP) watchdog time-out LOW time pulse (pin WDTON) debounce on VBAT LOW signal channel 0 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 1 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 2 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 3 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 4 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) Setting required IN02_MAP IN13_MAP INP_MAP ANDOR_MAP SEL_CURR_TRIP_CHAN CHAN_OT_FAULT_CLR CHAN_WD_MAP WD_TO CTRL_SET INT_PWM_FREQ PWM_DC_CH0 PWM_DC_CH1 PWM_DC_CH2 PWM_DC_CH3 PWM_DC_CH4 PWM_DC_CH5 PWM_DC_CH6 PWM_DC_CH7 OT_TRIPLEV_CH30 OT_TRIPLEV_CH74 IFSC_CH30 IFSC_CH74 IRQ_MAP CURR_TRIP_BLANKTIME DIG_OLTH DIG_FET CHAN_ALLOW_RETRY RETRY_SETTINGS WRITE_PROTECT WDPN_LOW_TIME VSBATLOW_DEB_EN NXIFSC_CH0 NXIFSC_CH1 NXIFSC_CH2 NXIFSC_CH3 NXIFSC_CH4
Register Name
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Table 35. -
Registers for mask options ...continued Description channel 5 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 6 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 7 ratio OCH and TONOCH trip level to Imeas(ADC)(fs) channel 0 FET configuration (high or low side) channel 1 FET configuration (high or low side) channel 2 FET configuration (high or low side) channel 3 FET configuration (high or low side) channel 4 FET configuration (high or low side) channel 5 FET configuration (high or low side) channel 6 FET configuration (high or low side) channel 7 FET configuration (high or low side) only high side available Setting required NXIFSC_CH5 NXIFSC_CH6 NXIFSC_CH7 HL_CH0 HL_CH1 HL_CH2 HL_CH3 HL_CH4 HL_CH5 HL_CH6 HL_CH7
Register Name
FIXED_GATE_SLEW_RATE rising and falling slew rate to have fixed or variable values during gate turn-on
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18. Package outline
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1
c
y X
A 48 49 33 32 ZE
e E HE wM pin 1 index bp 64 1 bp D HD wM ZD B vM B 16 vMA 17 Lp L detail X A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3 A1 0.25 0.10 A2 2.75 2.55 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.8 HD HE L 1.6 Lp 1.03 0.73 v 0.16 w 0.16 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 o 0
o
17.45 17.45 16.95 16.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 REFERENCES IEC 134E07 JEDEC MS-022 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-20
Fig 12. Package outline SOT393-1 (QFP64)
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19. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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19.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 36 and 37
Table 36. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 37. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13.
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Controller for TrenchPLUS FETs
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
20. Abbreviations
Table 38. Acronym ADC ASIC CDM EMC ESD FET HBM MOSFET PWM RF SPI Abbreviations Description Analog-to-Digital Converter Application Specific Integrated Circuit Charge Device Model ElectroMagnetic Compatibility ElectroStatic Discharge Field Effect Transistor Human Body Model Metal Oxide Semiconductor Field Effect Transistor Pulse-Width Modulation Radio Frequency Serial Peripheral Interface
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21. Revision history
Table 39. Revision history Release date 20080121 Data sheet status Product data sheet Change notice Supersedes BUK3F00-50WDXX_1 Document ID BUK3F00-50WDXX_2 Modifications: BUK3F00-50WDXX_1
*
Table 27, Vhys(uv)mod = module undervoltage hysteresis voltage: max value changed from 100 to 130. Product data sheet -
20071128
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22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
23. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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24. Contents
1 2 3 4 5 6 6.1 7 8 8.1 8.2 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.2 9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 7 Power and reference supplies. . . . . . . . . . . . . . 7 Battery supply: pins VBAT and GND . . . . . . . . . 7 Module supply: pins VCC(MOD) and GND. . . . . . 8 External logic supply: pins VCC(LOG)EXT and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog measurement supply: pins VCC(MEASC) and GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital supply: pins VCC(DIGC) and GND(DIGC). 8 Reference supplies: pins IREFCURR and IREFTEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Charge pump supply: pins VBAT(CP) and GND(CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Charge pump boost mode . . . . . . . . . . . . . . . . 9 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital control . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Peripheral Interface (SPI) . . . . . . . . . . . 12 SPI watchdog . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pulse-Width Modulation (PWM) . . . . . . . . . . . 15 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current measurement. . . . . . . . . . . . . . . . . . . 16 Current measurement circuits. . . . . . . . . . . . . 16 Analog current measurement output . . . . . . . 17 Digital current measurement output . . . . . . . . 17 Low battery supply voltage conditions . . . . . . 17 TrenchPLUS FET interface . . . . . . . . . . . . . . . 18 Overtemperature protection . . . . . . . . . . . . . . 18 Overcurrent protection . . . . . . . . . . . . . . . . . . 19 Gate inductive ring-off clamp . . . . . . . . . . . . . 20 Loss-of-ground protection. . . . . . . . . . . . . . . . 21 Controller settings. . . . . . . . . . . . . . . . . . . . . . 21 Open-circuit detection. . . . . . . . . . . . . . . . . . . 21 Channel selection . . . . . . . . . . . . . . . . . . . . . . 22 9.5.8 9.5.9 9.5.10 9.5.11 9.5.12 10 11 11.1 11.2 12 13 14 15 16 17 17.1 17.1.1 17.1.2 17.1.3 17.1.4 17.2 17.3 18 19 19.1 19.2 19.3 19.4 20 21 22 22.1 22.2 22.3 22.4 23 24 Mapping channels for direct channel control and PWM . . . . . . . . . . . . . . . . . . . . . . FET channel on/off control . . . . . . . . . . . . . . . Power dissipation . . . . . . . . . . . . . . . . . . . . . . Trip and retry . . . . . . . . . . . . . . . . . . . . . . . . . Trip-latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed functional settings . . . . . . . . . . . . . . . . Diagnostic functions . . . . . . . . . . . . . . . . . . . . Reset for interrupt and SPI watchdog . . . . . . Diagnostic data . . . . . . . . . . . . . . . . . . . . . . . Application design-in information . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . ElectroMagnetic Compatibility guidelines. . . . Ground layers. . . . . . . . . . . . . . . . . . . . . . . . . Circuit loops and tracks . . . . . . . . . . . . . . . . . Connector decoupling . . . . . . . . . . . . . . . . . . Module supply decoupling . . . . . . . . . . . . . . . ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . Additional metal mask options . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 24 24 25 27 27 27 30 32 33 34 35 41 41 41 41 41 41 41 43 45 46 46 46 46 47 48 49 50 50 50 50 50 50 51
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 January 2008 Document identifier: BUK3F00-50WDXX_2

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